1. Field of the Invention
The present invention generally relates to a transmission-line-voltage control circuit and an electronic device including the control circuit, and more particularly, to a transmission-line-voltage control circuit which controls a voltage level of a signal passing through a transmission line of an electronic device.
2. Description of the Prior Art
FIG. 1 shows a schematic diagram of an example of a conventional electronic device in which signals are transmitted through a transmission line such as a bus line.
The electronic device comprises a central processing unit (CPU) 1, and synchronous dynamic random-access memories (SDRAMs) 2 to 5, but in FIG. 1, only portions of each of the CPU 1 and the SDRAMs 2 to 5, namely data-output circuits 16 to 20 and data-input circuits 21 to 25, are illustrated. Each of output ports of the data-output circuits 16 to 20 and one each of input ports of the data-input circuits 21 to 25 are connected together to a respective one of data-input/output ports 6 to 10 of each of the CPU 1 and the SDRAMs 2 to 5. And the data-input/output ports 6 to 10 are respectively connected to a bus line 26 through respective stubs 27 to 31 of the bus line 26. Through the bus line 26, data DQ is transmitted, and is input to or output from the CPU 1 and the SDRAMs 2 to 5.
The electronic device further comprises a reference-voltage line 34 supplying a reference voltage Vref. The reference-voltage line 34 is connected to each of the other input ports of the data-input circuits 21 to 25 through respective reference-voltage input ports 11 to 15 of the CPU 1 and the SDRAMs 2 to 5. The data DQ input to the data-input circuits 21 to 25 is logically decided by comparing a voltage level of the data DQ with the reference voltage Vref.
Further, both end parts 35, 36 of the bus line 26 are terminated to the reference-voltage line 34 through terminating resistances 32, 33.
Next, a description will be given of a operation of the electronic device. In the electronic device, when the data DQ produced in the CPU 1 is transmitted to the SDRAM 2, the data DQ is output to the bus line 26 from the data-output circuit 16 through the data-input/output port 6 and the stub 27, and then the data DQ in the bus line 26 is input to the data-input circuit 22 of the SDRAM 2 through the stub 28 and the data-input/output port 7.
In general, when a signal waveform of the data DQ is transmitted through the bus line 26, a reflected signal waveform occurs at the end parts 35, 36 of the bus line 26, and the reflected signal waveform causes the main signal waveform of the data DQ to be distorted. However, in this electronic device, because the end parts 35, 36 of the bus line 26 are terminated by the terminating resistances 32, 33, a distortion of the signal waveform of the data DQ due to a reflection at the end parts 35, 36 may be reduced.
However, for example, when the data DQ produced in the CPU 1 is transmitted to the SDRAMs 2 to 5, the output ports of the data-output circuits 17 to 20 of the SDRAMs 2 to 5 are left in a high-impedance condition. In this condition, the output ports of the data-output circuits 17 to 20 are electrically in an open condition. Therefore, the signal waveform of the data DQ is reflected at respective opened output ports. A distortion of the signal waveform of the data DQ due to the reflection at the output ports of the data-output circuits 17 to 20 is relatively large compared to the distortion at the end parts 35, 36 which are terminated.
FIG. 2 shows a signal waveform of the data DQ passing through the bus line 26 in the conventional electronic device. In this drawing, as one example, it is shown that a level of the data DQ in the bus line 26 transits from a low level to a high level. In FIG. 2, a solid line 38 indicates the signal waveform of the data DQ in an ideal case of no reflection, a dotted line 39 indicates the signal waveform thereof in a case of a maximum acceptable reflection.
In this example, an ideal voltage level of the high level V.sub.OH is (Vref+0.6 V), and an ideal voltage level of the low level V.sub.OL is (Vref-0.6 V). And a high-level-side threshold level V.sub.IH is (Vref+0.1 V), and a low-level-side threshold level V.sub.IL is (Vref-0.1 V). In the data-input circuits 21 to 25, when the voltage level of the data DQ is in a value from V.sub.IH to V.sub.OH, the data DQ is logically decided to be the high level, whereas when the voltage level of the data DQ is in a value from V.sub.IL to V.sub.OL, the data DQ is logically decided to be the low level. A level range from V.sub.IL to V.sub.IH is a gray zone, in which an error decision may occur.
In this case, if acceptable margins of V.sub.OH, V.sub.OL, V.sub.IH and V.sub.IL are not taken into account, a maximum acceptable reflection ratio is represented as (V.sub.OH -V.sub.IH) /(V.sub.OH -V.sub.OL)=((Vref+0.6 V)-(Vref+0.1 V))/((Vref+0.6 V)-(Vref-0.6 V))=0.5 V/1.2 V=0.42. If the acceptable margins are taken into account, the maximum acceptable reflection ratio is further less than 0.42.
This result reveals that in this electronic device, a maximum reflection ratio at any port such as an output port of the data-output circuits 17 to 20 must be reduced to less than 0.42.
To reduce such a reflection, there is a method of connecting the terminating resistance at each end part in the SDRAM side of the stubs 27 to 31 which are connected to the respective output ports of the data-output circuits 16 to 20. In this method, because there is no opened end in a data transmission line, a distortion of the signal waveform of the data DQ due to the reflection may be negligibly reduced.
However, in this method, a load to be driven by the data-output circuits 16 to 20 becomes relatively small, so that a large driving ability is required of the data-output circuits 16 to 20. Thus, there is a problem that a size and a power consumption of such a data-output circuit are increased.
As mentioned above, it is found that it is difficult to directly reduce the reflection in the data transmission line by the terminating.
The electronic device shown in FIG. 1 has another problem. In a standby mode in which no data is supplied to the bus line, if the output ports of the data-output circuits 16 to 20 are left in the high-impedance condition to reduce the power consumption, a voltage level of the bus line 26 becomes uncertain. In this case, the data-input circuits 21 to 25 may not be regularly operative due to noise.
In this electronic device, to prevent this irregular operation of the data-input circuits 21 to 25, one of the data-output circuits 16 to 20, for example, the data-output circuit 16, may be activated to produce, for example, the low level, as the data DQ, during the standby mode. However, there is also a problem that the power consumption in the standby mode is increased.